1. Field of the Invention
This invention relates to a liquid crystal display device. More particularly, this invention relates to a liquid crystal display device that simplifies a wiring structure of a flexible printed substrate for supplying driving signals to a driver IC mounted by a flip chip mounting system and reduces a cost by employing a novel signal transmission system.
2. Description of the Related Art
Liquid crystal display devices have been wide spread as a display device for various image displaying apparatuses. An active matrix type liquid crystal display device, that has an active cell such as a thin film transistor TFT for each pixel and switches and drives the active cell, applies a liquid crystal driving voltage (gray scale voltage) to a pixel electrode through the active cell. Therefore, this liquid crystal display device is free from cross-talk between the pixels and can conduct multiple gray scale display without employing a specific driving method for preventing cross-talk that has been necessary in a simple matrix type liquid crystal display device.
FIG. 42 of the accompanying drawings is a block diagram useful for explaining a structural example of a driving circuit in an active matrix type liquid crystal display device. FIGS. 43A, 43B, 44A and 44B are explanatory views (signal time charts) for explaining horizontal direction timing and vertical direction timing of display control in FIG. 42.
As shown in FIG. 42, the liquid crystal display device includes an interface substrate (a rigid printed substrate) having mounted thereto an interface circuit that receives display data (which will be called also “pixel data”) and a control signal from a host computer, and applies pixel data, various clock signals and various driving voltages to a liquid crystal panel TFT-LCD.
The interface circuit has a display control device equipped with a timing converter TCON and a power supply circuit. The display control device outputs timing signals such as a data bus for transmitting image data, a data bus for transferring a second pixel, a clock D2 (CL2) required for a drain driver to acquire pixel data (which will be called merely “data”, too), a clock D1 (CL1) required for the drain driver to switch a liquid crystal driving signal, a frame starting direction signal for driving a gate driver and a gate clock (clock G), to the liquid crystal panel.
The power supply circuit includes a positive gray scale voltage generating circuit, a negative gray scale voltage generating circuit, a voltage generating circuit for counter electrodes and a voltage generating circuit for gate electrodes.
The number of display pixels of the liquid crystal panel constituting the liquid crystal display device shown in FIG. 42 is (1,024×3 in a lateral direction)×(768 in a longitudinal direction). A liquid crystal panel having higher resolution is known, too. The interface substrate for receiving the display data and the control signals from the host computer receives data in pixel unit, that is, data of each of red (R), green (G) and blue (b) as a set, and transfers (or transmits) one pixel data set in a unit time to the drain driver through data lines shown in FIG. 38.
The host computer transmits a clock signal as the reference of the unit time to the liquid crystal display device. More concretely, the liquid crystal display device having 1,024×768 pixels of this structural example uses ordinarily a frequency of 65 MHz.
The liquid crystal panel TFT-LCD has a construction such that the drain drivers (called also “TFT drivers”) arc situated in the lateral direction with the display screen as the reference. The drain drivers are connected to the drain lines of the thin film transistors TFT to supply a voltage for driving the liquid crystal. The gate drivers are connected to the gate lines, and a voltage is supplied to the gates of the thin film transistors TFT for a certain predetermined time (one horizontal operation time).
A timing converter comprises a semiconductor integrated circuit (LSI), receives the display data and the control signals from the host computer and outputs necessary display data and operation clocks to the gate drivers on the basis of them. Incidentally, the data line for one pixel has 18 bits (six bits for each of R, G and B).
The host computer transmits signals to the timing converter of the liquid crystal display device by low voltage amplification differential signals, or so-called “LVDS”. The timing converter transmits the signals at a CMOS level to the drain drivers. However, it is difficult in this case to supply 65 MHz pixel clocks. Therefore, the display date is transmitted in synchronism with both edges of the rise and fall of a 32.5 MHz clock.
As shown in FIGS. 43A, 43B, 44A and 44B, pulses of one horizontal time cycle are given to the gate drivers on the basis of the horizontal synchronizing (sync) signal and the display timing signal so as to supply voltages to the gate lines of the thin film transistors TFT in each horizontal time. The frame starting direction signal is given, too, on the basis of the vertical sync signal so that display can be made from the first line in one frame time unit.
The positive gray scale voltage generating circuit and the negative gray scale voltage generating circuit of the power supply circuit generate a reference voltage for converting a voltage, that is to be given to the liquid crystal in every certain time, to an alternating current. This alteration is conducted in practice as the positive gray scale voltage and the negative gray scale voltage are alternately switched and used inside the drain driver. Incidentally, the term “alteration” used hereby means alternation of the voltage to be given to the drain driver to the positive voltage side/negative voltage side in every predetermined time. Here, the cycle of this alteration corresponds to one frame time unit.
The flip chip system described above is also called an “FCA system”. This FCA system is the one that directly mounts the driving IC (drain drivers and gate drivers) to the outer periphery of one of the substrates of the liquid crystal panel (generally, the lower substrate), and is also called a “chip-on-glass system (COG)”. Various signals and an operation power source to the driving IC (drain drivers and gate drivers) directly mounted to the substrate of the liquid crystal panel are supplied through the flexible printed substrate FPC connected to the interface substrate.
FIG. 45 is an explanatory of a mounting example of a drain driver and a gate driver of a liquid crystal display device and an interface substrate. A drain line side flexible printed substrate FPC2 is fitted to one of the edges (to the lower edge in the drawing, a side in a major direction) of a liquid crystal panel PNL formed by bonding a lower substrate SUB1 and an upper substrate SUB2, and is folded to the back of the liquid crystal panel PNL along the arrangement of an open portion HOP.
A gate line side flexible printed substrate FPC1 is fitted to the left edge (the left edge in the drawing, or a side in a minor direction), and its connector CT3, a connector CTR3 of the interface substrate PCB and a connector CTR4 connected to a connector CT4 of the drain line side flexible printed substrate FPC2 are coupled with one another. An interface connector CT1 for connecting signals from the host computer, a timing converter TCON, and so forth, are further fitted to this substrate FPC1. Incidentally, this example employs the data transfer system of an LVDS system. A reception side signal converter (LVDS-R) necessary in this case is integrated with the same chip as that of the timing converter TCON to reduce the mounting area on the interface substrate.
An upper polarizer POL1 is bonded to the surface side of the liquid crystal panel PNL (to the surface of the upper substrate SUB2) and a display area AR is formed inside the upper polarizer POL1.
The chip IC2 mounted to the outer edge of the lower side of the lower substrate is the drain driver and the chip IC1 mounted to the outer edge of the left side is the gate driver. Symbol FGP represents a frame ground pad and FHL does a positioning hole.